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1 ? CA3140, CA3140a 4.5mhz, bimos operational amplifier with mosfet input/bipolar output the CA3140a and CA3140 are integrated circuit operational amplifiers that combine the advantages of high voltage pmos transistors with high voltage bipolar transistors on a single monolithic chip. the CA3140a and CA3140 bimos operational amplifiers feature gate protected mosfet (pmos) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. the CA3140a and CA3140 operate at supply voltage from 4v to 36v (either single or dual supply). these operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. terminals are also provided for use in applications requiring input offset voltage nulling. the use of pmos field effect transistors in the input stage results in common mode input voltage capability down to 0.5v below the negative supply terminal, an important attribute for single supply applications. the output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground. the CA3140a and CA3140 are intended for operation at supply voltages up to 36v ( 18v). features ? mosfet input stage - very high input impedance (z in ) -1.5t ? (typ) - very low input current (i l ) -10pa (typ) at 15v - wide common mode input voltage range (v lcr ) - can be swung 0.5v below negative supply voltage rail - output swing complements input common mode range ? directly replaces industry type 741 in most ?applications applications ? ground-referenced single supply amplifiers in automobile and portable instrumentation ? sample and hold amplifiers ? long duration timers/multivibrators ( seconds-minutes-hours) ? photocurrent instrumentation ? peak detectors ? active filters ? comparators ? interface in 5v ttl systems and other low supply voltage systems ? all standard operational amplifier applications ? function generators ? tone controls ? power supplies ? portable instruments ? intrusion alarm systems pinout CA3140 (pdip, soic) top view ordering information part number (brand) temp. range ( o c) package pkg. no. CA3140ae -55 to 125 8 ld pdip e8.3 CA3140am (3140a) -55 to 125 8 ld soic m8.15 CA3140e -55 to 125 8 ld pdip e8.3 CA3140m (3140) -55 to 125 8 ld soic m8.15 CA3140m96 (3140) -55 to 125 8 ld soic tape and reel inv. input non-inv. v- 1 2 3 4 8 7 6 5 strobe v+ output offset null offset null input - + data sheet november 2002 fn957.7 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute maximum ratings thermal information dc supply voltage (between v+ and v- terminals) . . . . . . . . . 36v differential mode input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8v dc input voltage . . . . . . . . . . . . . . . . . . . . . (v+ +8v) to (v- -0.5v) input terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma output short circuit duration (note 2) . . . . . . . . . . . . . . indefinite operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 115 n/a soic package . . . . . . . . . . . . . . . . . . . 165 n/a maximum junction temperature (plastic package) . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 fo r details 2. short circuit may be applied to ground or to either supply. electrical specifications v supply = 15v, t a = 25 o c parameter symbol test conditions typical values units CA3140 CA3140a input offset voltage adjustment resistor typical value of resistor between terminals 4 and 5 or 4 and 1 to adjust max v io 4.7 18 k ? input resistance r i 1.5 1.5 t ? input capacitance c i 44pf output resistance r o 60 60 ? equivalent wideband input noise voltage (see figure 27) e n bw = 140khz, r s = 1m ? 48 48 v equivalent input noise voltage (see figure 35) e n r s = 100 ? f = 1khz 40 40 nv/ hz f = 10khz 12 12 nv/ hz short circuit current to opposite supply i om + source 40 40 ma i om -sink1818ma gain-bandwidth product, (see figures 6, 30) f t 4.5 4.5 mhz slew rate, (see figure 31) sr 9 9 v/ s sink current from terminal 8 to terminal 4 to swing output low 220 220 a transient response (see figure 28) t r r l = 2k ? c l = 100pf rise time 0.08 0.08 s os overshoot 10 10 % settling time at 10v p-p , (see figure 5) t s r l = 2k ? c l = 100pf voltage follower to 1mv 4.5 4.5 s to 10mv 1.4 1.4 s electrical specifications for equipment design, at v supply = 15v, t a = 25 o c, unless otherwise specified parameter symbol CA3140 CA3140a units min typ max min typ max input offset voltage |v io |- 5 15- 2 5mv input offset current |i io | - 0.5 30 - 0.5 20 pa input current i i - 10 50 - 10 40 pa large signal voltage gain (note 3) (see figures 6, 29) a ol 20 100 - 20 100 - kv/v 86 100 - 86 100 - db CA3140, CA3140a
3 common mode rejection ratio (see figure 34) cmrr - 32 320 - 32 320 v/v 70 90 - 70 90 - db common mode input voltage range (see figure 8) v icr -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 v power-supply rejection ratio, ? v io / ? v s (see figure 36) psrr - 100 150 - 100 150 v/v 76 80 - 76 80 - db max output voltage (note 4) (see figures 2, 8) v om + +12 13 - +12 13 - v v om - -14 -14.4 - -14 -14.4 - v supply current (see figure 32) i+ - 4 6 - 4 6 ma device dissipation p d - 120 180 - 120 180 mw input offset voltage temperature drift ? v io / ? t- 8 - - 6 - v/ o c notes: 3. at v o = 26v p-p , +12v, -14v and r l = 2k ? . 4. at r l = 2k ? . electrical specifications for equipment design, at v supply = 15v, t a = 25 o c, unless otherwise specified (continued) parameter symbol CA3140 CA3140a units min typ max min typ max electrical specifications for design guidance at v+ = 5v, v- = 0v, t a = 25 o c parameter symbol typical values units CA3140 CA3140a input offset voltage |v io |5 2mv input offset current |i io |0.1 0.1pa input current i i 22pa input resistance r i 11t ? large signal voltage gain (see figures 6, 29) a ol 100 100 kv/v 100 100 db common mode rejection ratio cmrr 32 32 v/v 90 90 db common mode input voltage range (see figure 8) v icr -0.5 -0.5 v 2.6 2.6 v power supply rejection ratio psrr ? v io / ? v s 100 100 v/v 80 80 db maximum output voltage (see figures 2, 8) v om +3 3 v v om -0.13 0.13 v maximum output current: source i om +10 10ma sink i om -1 1ma slew rate (see figure 31) sr 7 7 v/ s gain-bandwidth product (see figure 30) f t 3.7 3.7 mhz supply current (see figure 32) i+ 1.6 1.6 ma device dissipation p d 88mw sink current from terminal 8 to terminal 4 to swing output low 200 200 a CA3140, CA3140a
4 block diagram schematic diagram a 10 a 10,000 c 1 12pf 5 a 1 1 8 4 6 7 2 3 offset strobe null output input + - 200 a200 a 1.6ma 2 a2ma 2ma 4ma v+ v- bias circuit current sources and regulator r 5 500 ? r 4 500 ? q 11 q 12 r 2 500 ? r 3 500 ? q 10 q 9 d 5 d 4 d 3 5 1 8 strobe offset null 3 2 non-inverting input inverting input + - c 1 12pf q 13 q 15 q 16 q 21 q 20 d 8 q 19 q 18 q 17 r 11 20 ? r 9 50 ? r 8 1k r 12 12k r 14 20k r 13 5k d 7 r 10 1k output d 6 4 v- v+ 6 7 dynamic current sink output stage second stage input stage bias circuit d 2 q 8 q 4 q 3 q 5 q 2 q 6 q 7 d 1 q 1 r 1 8k q 14 r 7 30 ? r 6 50 ? note: all resistance values are in ohms. CA3140, CA3140a
5 application information circuit description as shown in the block diagram, the input terminals may be operated down to 0.5v below the negative supply rail. two class a amplifier stages provide the voltage gain, and a unique class ab amplifier stage provides the current gain necessary to drive low-impedance loads. a biasing circuit provides control of cascoded constant current flow circuits in the first and second stages. the CA3140 includes an on chip phase compensating capacitor that is sufficient for the unity gain voltage follower configuration. input stage the schematic diagram consists of a differential input stage using pmos field-effect transistors (q 9 , q 10 ) working into a mirror pair of bipolar transistors (q 11 , q 12 ) functioning as load resistors together with resistors r 2 through r 5 . the mirror pair transistors also function as a differential-to-single-ended converter to provide base current drive to the second stage bipolar transistor (q 13 ). offset nulling, when desired, can be effected with a 10k ? potentiometer connected across terminals 1 and 5 and with its slider arm connected to terminal 4. cascode-connected bipolar transistors q 2 , q 5 are the constant current source for the input stage. the base biasing circuit for the constant current source is described subsequently. the small diodes d 3 , d 4 , d 5 provide gate oxide protection against high voltage transients, e.g., static electricity. second stage most of the voltage gain in the CA3140 is provided by the second amplifier stage, consisting of bipolar transistor q 13 and its cascode connected load resistance provided by bipolar transistors q 3 , q 4 . on-chip phase compensation, sufficient for a majority of the applications is provided by c 1 . additional miller-effect compensation (roll off) can be accomplished, when desired, by simply connecting a small capacitor between terminals 1 and 8. terminal 8 is also used to strobe the output stage into quiescence. when terminal 8 is tied to the negative supply rail (terminal 4) by mechanical or electrical means, the output terminal 6 swings low, i.e., approximately to terminal 4 potential. output stage the CA3140 series circuits employ a broad band output stage that can sink loads to the negative supply to complement the capability of the pmos input stage when operating near the negative rail. quiescent current in the emitter-follower cascade circuit (q 17 , q 18 ) is established by transistors (q 14 , q 15 ) whose base currents are ?mirrored? to current flowing through diode d 2 in the bias circuit section. when the CA3140 is operating such that output terminal 6 is sourcing current, transistor q 18 functions as an emitter-follower to source current from the v+ bus (terminal 7), via d 7 , r 9 , and r 11 . under these conditions, the collector potential of q 13 is sufficiently high to permit the necessary flow of base current to emitter follower q 17 which, in turn, drives q 18 . when the CA3140 is operating such that output terminal 6 is sinking current to the v- bus, transistor q 16 is the current sinking element. transistor q 16 is mirror connected to d 6 , r 7 , with current fed by way of q 21 , r 12 , and q 20 . transistor q 20 , in turn, is biased by current flow through r 13 , zener d 8 , and r 14 . the dynamic current sink is controlled by voltage level sensing. for purposes of explanation, it is assumed that output terminal 6 is quiescently established at the potential midpoint between the v+ and v- supply rails. when output current sinking mode operation is required, the collector potential of transistor q 13 is driven below its quiescent level, thereby causing q 17 , q 18 to decrease the output voltage at terminal 6. thus, the gate terminal of pmos transistor q 21 is displaced toward the v- bus, thereby reducing the channel resistance of q 21 . as a consequence, there is an incremental increase in current flow through q 20 , r 12 , q 21 , d 6 , r 7 , and the base of q 16 . as a result, q 16 sinks current from terminal 6 in direct response to the incremental change in output voltage caused by q 18 . this sink current flows regardless of load; any excess current is internally supplied by the emitter-follower q 18 . short circuit protection of the output circuit is provided by q 19 , which is driven into conduction by the high voltage drop developed across r 11 under output short circuit conditions. under these conditions, the collector of q 19 diverts current from q 4 so as to reduce the base current drive from q 17 , thereby limiting current flow in q 18 to the short circuited load terminal. bias circuit quiescent current in all stages (except the dynamic current sink) of the CA3140 is dependent upon bias current flow in r 1 . the function of the bias circuit is to establish and maintain constant current flow through d 1 , q 6 , q 8 and d 2 . d 1 is a diode connected transistor mirror connect ed in parallel with the base emitter junctions of q 1 , q 2 , and q 3 . d 1 may be considered as a current sampling diode that senses the emitter current of q 6 and automatically adjusts the base current of q 6 (via q 1 ) to maintain a constant current through q 6 , q 8 , d 2 . the base currents in q 2 , q 3 are also determined by constant current flow d 1 . furthermore, current in diode connected transistor q 2 establishes the currents in transistors q 14 and q 15 . typical applications wide dynamic range of input and output characteristics with the most desirable high input impedance characteristics is achieved in the CA3140 by the use of an unique design based upon the pmos bipolar process. input common mode voltage range and output swing capabilities are complementary, allowing operation with the single supply down to 4v. the wide dynamic range of these parameters also means that this device is suitable for many single supply applications, such as, for example, where one input is driven below the potential of terminal 4 and the phase sense of the output signal must be maintained ? a most important consideration in comparator applications. CA3140, CA3140a
6 output circuit considerations excellent interfacing with ttl circuitry is easily achieved with a single 6.2v zener diode connected to terminal 8 as shown in figure 1. this connection assures that the maximum output signal swing will not go more positive than the zener voltage minus two base-to-emitter voltage drops within the CA3140. these voltages are independent of the operating supply voltage. figure 2 shows output current sinking capabilities of the CA3140 at various supply voltages. output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for level shifting circuitry usually associated with the 741 series of operational amplifiers. figure 4 shows some typical configurations. note that a series resistor, r l , is used in both cases to limit the drive available to the driven device. moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit. offset voltage nulling the input offset voltage can be nulled by connecting a 10k ? potentiometer between terminals 1 and 5 and returning its wiper arm to terminal 4, see figure 3a. this technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. typical values of series resistors (r) that may be placed at either end of the potentiometer, see figure 3b, to optimize its utilization range are given in the electrical specifications table. an alternate system is shown in figure 3c. this circuit uses only one additional resistor of approximately the value shown in the table. for potentiometers, in which the resistance does not drop to 0 ? at either end of rotation, a value of resistance 10% lower than the values shown in the table should be used. low voltage operation operation at total supply voltages as low as 4v is possible with the CA3140. a current regulator based upon the pmos threshold voltage maintains reasonable constant operating current and hence consistent performance down to these lower voltages. the low voltage limitation occurs when the upper extreme of the input common mode voltage range extends down to the voltage at terminal 4. this limit is reached at a total supply voltage just below 4v. the output voltage range also begins to extend down to the negative supply rail, but is slightly higher than that of the input. figure 8 shows these characteristics and shows that with 2v dual supplies, the lower extreme of the input common mode voltage range is below ground potential. 3 2 4 CA3140 8 6 7 v+ 5v to 36v 6.2v 5v logic supply 5v typical ttl gate figure 1. zener clamping diode connected to terminals 8 and 4 to limit CA3140 output swing to ttl levels 1 0.01 0.1 load (sinking) current (ma) 1.0 10 10 100 1000 output stage transistor (q 15 , q 16 ) saturation voltage (mv) supply voltage (v-) = 0v t a = 25 o c supply voltage (v+) = +5v +15v +30v figure 2. voltage across output transistors (q 15 and q 16 ) vs load current figure 3a. basic figure 3b. improved resolution figure 3c. simpler improved resolution figure 3. three offset voltage nulling methods 3 2 4 CA3140 7 6 v+ 5 1 v- 10k ? 3 2 4 CA3140 7 6 v+ 5 1 v- 10k ? r r 3 2 4 CA3140 7 6 v+ 5 1 v- 10k ? r CA3140, CA3140a
7 bandwidth and slew rate for those cases where bandwidth reduction is desired, for example, broadband noise reduction, an external capacitor connected between terminals 1 and 8 can reduce the open loop -3db bandwidth. the slew rate will, however, also be proportionally reduced by using this additional capacitor. thus, a 20% reduction in bandwidth by this technique will also reduce the slew rate by about 20%. figure 5 shows the typical settling time required to reach 1mv or 10mv of the final value for various levels of large signal inputs for the voltage follower and inverting unity gain amplifiers. the exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of the CA3140; as shown in figure 6. input circuit considerations as mentioned previously, the amplifier inputs can be driven below the terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1ma to prevent damage to the input protection circuitry. moreover, some current limiting resistance should be provided between the inverting input and the output when figure 4. methods of utilizing the v ce(sat) sinking current capability of the CA3140 series 3 2 4 CA3140 7 6 load r l r s mt 2 mt 1 30v no load 120v ac 3 2 4 CA3140 7 6 v+ +hv load r l figure 5a. waveform figure 5b. test circuits figure 5. settling time vs input voltage settling time ( s) 0.1 input voltage (v) 1.0 10 supply voltage: v s = 15v t a = 25 o c 1mv 10mv 10mv 1mv 1mv 1mv 10mv follower inverting load resistance (r l ) = 2k ? load capacitance (c l ) = 100pf 10 8 6 4 2 0 -2 -4 -6 -8 -10 10mv 3 2 CA3140 6 simulated load 4 -15v 0.1 f 5.11k ? 0.1 f 7 +15v 5k ? 2k ? 100pf 5k ? inverting settling point 200 ? 4.99k ? d 1 1n914 d 2 1n914 2 CA3140 6 simulated load 4 -15v 0.1 f 0.1 f 7 +15v 2k ? 100pf 0.05 f 2k ? 3 10k ? follower CA3140, CA3140a
8 the CA3140 is used as a unity gain voltage follower. this resistance prevents the possibility of extremely large input signal transients from forcing a signal through the input protection network and directly driving the internal constant current source which could result in positive feedback via the output terminal. a 3.9k ? resistor is sufficient. the typical input current is on the order of 10pa when the inputs are centered at nominal device dissipation. as the output supplies load current, device dissipation will increase, raising the chip temperature and resulting in increased input current. figure 7 shows typical input terminal current versus ambient temperature for the CA3140. it is well known that mosfet devices can exhibit slight changes in characteristics (for example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over long periods at elevated temperatures. both applied voltage and temperature accelerate these changes. the process is reversible and offset voltage shifts of the opposite polarity reverse the offset. figure 9 shows the typical offset voltage change as a function of various stress voltages at the maximum rating of 125 o c (for metal can); at lower temperatures (metal can and plastic), for example, at 85 o c, this change in voltage is considerably less. in typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. figure 6. open loop voltage gain and phase vs frequency figure 7. input current vs temperature figure 8. output voltage swing capability and comm on mode input voltage range vs supply voltage 10 1 10 3 10 4 10 5 10 6 10 7 10 8 frequency (hz) o pen l oo p v o lta g e g ain ( db ) 100 80 60 40 20 0 supply voltage: v s = 15v t a = 25 o c 10 2 open loop phase -75 -90 -105 -120 -135 -150 (degrees) r l = 2k ? , c l = 0pf r l = 2k ? , c l = 100pf ol supply voltage: v s = 15v temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 input current (pa) 1k 100 1 10k 10 supply voltage (v+, v-) 0 5 10 15 20 25 -1.5 -2.0 -1.0 -2.5 r l = +v out at t a = 125 o c +v out at t a = 25 o c +v out at t a = -55 o c +v icr at t a = 125 o c +v icr at t a = 25 o c +v icr at t a = -55 o c -3.0 0 -0.5 input and o utput v o lta g e ex c ur s i o n s from terminal 7 (v+) supply voltage (v+, v-) 0 5 10 15 20 25 -v icr at t a = 125 o c -v icr at t a = 25 o c -v icr at t a = -55 o c -v out for t a = -55 o c to 125 o c input and output voltage excursions from terminal 4 (v-) 0 -0.5 0.5 -1.0 -1.5 1.5 1.0 CA3140, CA3140a
9 super sweep function generator a function generator having a wide tuning range is shown in figure 10. the 1,000,000/1 adjustment range is accomplished by a single variable potentiometer or by an auxiliary sweeping signal. the CA3140 functions as a non- inverting readout amplifier of the triangular signal developed across the integrating capacitor network connected to the output of the ca3080a current source. buffered triangular output signals are then applied to a second ca3080 functioning as a high speed hysteresis switch. output from the switch is returned directly back to the input of the ca3080a current source, thereby, completing the positive feedback loop the triangular output level is determined by the four 1n914 level limiting diodes of the second ca3080 and the resistor divider network connected to terminal no. 2 (input) of the ca3080. these diodes establish the input trip level to this switching stage and, therefore, indirectly determine the amplitude of the output triangle. compensation for propagation delays around the entire loop is provided by one adjustment on the input of the ca3080. this adjustment, which provides for a constant generator amplitude output, is most easily made while the generator is sweeping. high frequency ramp linearity is adjusted by the single 7pf to 60pf capacitor in the output of the ca3080a. it must be emphasized that only the ca3080a is characterized for maximum output linearity in the current generator function. meter driver and buffer amplifier figure 11 shows the CA3140 connected as a meter driver and buffer amplifier. low driving impedance is required of the ca3080a current source to assure smooth operation of the frequency adjustment control. this low-driving impedance requirement is easily met by using a CA3140 connected as a voltage follower. moreover, a meter may be placed across the input to the ca3080a to give a logarithmic analog indication of the function generator?s frequency. analog frequency readout is readily accomplished by the means described above because the output current of the ca3080a varies approximately one decade for each 60mv change in the applied voltage, v abc (voltage between terminals 5 and 4 of the ca3080a of the function generator). therefore, six decades represent 360mv change in v abc . now, only the reference voltage must be established to set the lower limit on the meter. the three remaining transistors from the ca3086 array used in the sweep generator are used for this reference voltage. in addition, this reference generator arrangement tends to track ambient temperature variations, and thus compensates for the effects of the normal negative temperature coefficient of the ca3080a v abc terminal voltage. another output voltage from the reference generator is used to insure temperature tracking of the lower end of the frequency adjustment potentiometer. a large series resistance simulates a current source, assuring similar temperature coefficients at both ends of the frequency adjustment control. to calibrate this circuit, set the frequency adjustment potentiometer at its low end. then adjust the minimum frequency calibration control for the lowest frequency. to establish the upper frequency limit, set the frequency adjustment potentiometer to its upper end and then adjust the maximum frequency calibration control for the maximum frequency. because there is interaction among these controls, repetition of the adjustment procedure may be necessary. two adjustments are used for the meter. the meter sensitivity control sets the meter scale width of each decade, while the meter position control adjusts the pointer on the scale with negligible effect on the sensitivity adjustment. thus, the meter sensitivity adjustment control calibrates the meter so that it deflects 1 / 6 of full scale for each decade change in frequency. sine wave shaper the circuit shown in figure 12 uses a CA3140 as a voltage follower in combination with diodes from the ca3019 array to convert the triangular signal from the function generator to a sine-wave output signal having typically less than 2% thd. the basic zero crossing slope is established by the 10k ? potentiometer connected between terminals 2 and 6 of the CA3140 and the 9.1k ? resistor and 10k ? potentiometer from terminal 2 to ground. two break points are established by diodes d 1 through d 4 . positive feedback via d 5 and d 6 establishes the zero slope at the maximum and minimum levels of the sine wave. this technique is necessary because the voltage follower configuration approaches unity gain rather than the zero gain required to shape the sine wave at the two extremes. 7 6 5 4 3 2 0 offset voltage shift (mv) 0 500 1000 1500 2000 2500 3000 3500 4000 4500 time (hours) 1 differential dc voltage (across terminals 2 and 3) = 0v output voltage = v+ / 2 t a = 125 o c for metal can packages differential dc voltage (across terminals 2 and 3) = 2v output stage toggled figure 9. typical incremental offset voltage shift vs operating life CA3140, CA3140a
10 figure 10a. circuit top trace: output at junction of 2.7 ? and 51 ? resistors; 5v/div., 500ms/div. center trace: external output of triangular function generator; 2v/div., 500ms/div. bottom trace: output of ?log? generator; 10v/div., 500ms/div. figure 10b. figure function generator sweeping 1v/div., 1s/div. three tone test signals, highest frequency 0.5mhz. note the slight asymmetry at the three second/cycle signal. this asymmetry is due to slightly different positive and negative integration from the ca3080a and from the pc board and component leakages at the 100pa level. figure 10c. function generator with fixed frequencies figure 10d. interconnections figure 10. function generator 0.1 f 1n914 6 7 4 2 3 0.1 f 5.1k ? 10k ? 2.7k ? 6 7 4 2 5 -15v 13k ? +15v centering 10k ? -15v 910k ? 62k ? 11k ? 10k ? external output 11k ? high frequency level 7-60pf external output to output amplifier output amplifier to sine wave shaper 2k ? frequency adjustment high freq. shape symmetry this network is used when the optional buffer circuit is not used -15v +15v 10k ? 120 ? 39k ? 100k ? 3 6 3 2 4 7 7.5k ? +15v +15v 15k ? 360 ? 360 ? 2m ? 7-60 pf -15v -15v +15v 51 pf + ca3080a - CA3140 ca3080 + - + - 5 -15v from buffer meter driver (optional) frequency adjustment meter driver and buffer amplifier function generator sine wave shaper m power supply 15v -15v +15v dc level adjust 51 ? wideband line driver sweep generator gate sweep v- sweep length external input off v- coarse rate fine rate ext. int. CA3140, CA3140a
11 figure 11. meter driver and buffer amplifier figure 12. sine wave shaper figure 13. sweeping generator frequency calibration minimum 200 a meter frequency calibration maximum meter sensitivity adjustment meter position adjustment ca3080a 6 3 2 4 7 + CA3140 - frequency adjustment 10k ? 620 ? 4.7k ? 0.1 f 12k ? 2k ? 500k ? 620k ? 51k ? 3m ? 510 ? 510 ? 2k ? 3.6k ? -15v m 11 14 13 3 / 5 of ca3086 5 4 to ca3080a of function generator (figure 10) 7 8 6 9 1k ? 2.4k ? 2.5 k ? +15v sweep in 10 12 6 3 2 4 7 + CA3140 - 7 2 8 5 6 1 4 3 9 5.1k ? 0.1 f -15v d 1 d 4 d 2 d 3 d 6 d 5 ca3019 diode array external output +15v +15v -15v 100 k ? substrate of ca3019 to wideban d output amplifier 7.5k ? 5.6k ? -15v r3 10k ? 10k ? 0.1 f 1m ? 9.1k ? r 1 10k ? r 2 1k ? 430 ? 4 7 + CA3140 - 0.1 +15v - 15v 2 3 6 f 0.1 f coarse rate sawtooth symmetry 0.47 f 0.047 f 4700pf 470pf 7 3 2 6 4 + CA3140 - 5 1 3 2 4 1 5 51k ? 6.8k ? 91k ? 10k ? 100 ? 390 ? 3.9 ? 25k ? +15v -15v 10k ? 10k ? 100k ? 30k ? 43k ? log vio 50k ? log rate 10k ? gate pulse output -15v external output to function generator ?sweep in? sweep width to output amplifier 36k ? 51k ? 75k ? 50k ? sawtooth ?log? triangle +15v +15v 4 7 + CA3140 - 3 2 6 +15v transistors from ca3086 array adjust triangle sawtooth ?log? 8.2k ? 100k ? 100k ? fine rate sawtooth 22m ? 1m ? 18m ? 750k ? ?log? 1n914 1n914 sawtooth and ramp low level set (-14.5v) -15v CA3140, CA3140a
12 this circuit can be adjusted most easily with a distortion analyzer, but a good first approximation can be made by comparing the output signal with that of a sine wave generator. the initial slope is adjusted with the potentiometer r 1 , followed by an adjustment of r 2 . the final slope is established by adjusting r 3 , thereby adding additional segments that are contributed by these diodes. because there is some interaction among these controls, repetition of the adjustment procedure may be necessary. sweeping generator figure 13 shows a sweeping generator. three CA3140s are used in this circuit. one CA3140 is used as an integrator, a second device is used as a hysteresis switch that determines the starting and stopping points of the sweep. a third CA3140 is used as a logarithmic shaping network for the log function. rates and slopes, as well as sawtooth, triangle, and logarithmic sweeps are generated by this circuit. wideband output amplifier figure 14 shows a high slew rate, wideband amplifier suitable for use as a 50 ? transmission line driver. this circuit, when used in conjunction with the function generator and sine wave shaper circuits shown in figures 10 and 12 provides 18v p-p output open circuited, or 9v p-p output when terminated in 50 ? . the slew rate required of this amplifier is 28v/ s (18v p-p x x 0.5mhz). power supplies high input impedance, common mode capability down to the negative supply and high output drive current capability are key factors in the design of wide range output voltage supplies that use a single input voltage to provide a regulated output voltage that can be adjusted from essentially 0v to 24v. unlike many regulator systems using comparators having a bipolar transistor input stage, a high impedance reference voltage divider from a single supply can be used in connection with the CA3140 (see figure 15). essentially, the regulators, shown in figures 16 and 17, are connected as non inverting power operational amplifiers with a gain of 3.2. an 8v reference input yields a maximum output voltage slightly greater than 25v. as a voltage follower, when the reference input goes to 0v the output will be 0v. because the offset voltage is also multiplied by the 3.2 gain factor, a potentiometer is needed to null the offset voltage. series pass transistors with high i cbo levels will also prevent the output voltage from reaching zero because there is a finite voltage drop (v cesat ) across the output of the CA3140 (see figure 2). this saturation voltage level may indeed set the lowest voltage obtainable. the high impedance presented by terminal 8 is advantageous in effecting current limiting. thus, only a small signal transistor is required for the current-limit sensing amplifier. resistive decoupling is provided for this transistor to minimize damage to it or the CA3140 in the event of unusual input or output transients on the supply rail. figures 16 and 17, show circuits in which a d2201 high speed diode is used for the current sensor. this diode was chosen for its slightly higher forward voltage drop characteristic, thus giving greater sensitivity. it must be emphasized that heat sinking of this diode is essential to minimize variation of the current trip point due to internal heating of the diode. that is, 1a at 1v forward drop represent s one watt which can result in significant regenerative changes in the current trip point as the diode temperature rises. placing the small signal reference amplifier in the proximity of the current sensing diode also helps minimize the variability in the trip level due to the negative temperature coefficient of the diode. in spite of those limitations, the current limiting point can easily be adjusted over the range from 10ma to 1a with a single adjustment potentiometer. if the temperat ure stability of the current limiting system is a serious consideration, the more usual current sampling resistor type of circuitry should be employed. a power darlington transistor (in a metal can with heatsink), is used as the series pass element for the conventional current limiting system, figure 16, because high power darlington dissipation will be encountered at low output voltage and high currents. 2 6 8 1 4 7 + CA3140 - 50 f 25v 2.2 k ? 2n3053 1n914 2.2 k ? 1n914 2.7 ? 2.7 ? 2n4037 + - + - 50 f 25v 3 signal level adjustment 2.5k ? 200 ? 2.4pf 2pf -15v +15v output dc level adjustment -15v +15v 3k ? 200 ? 1.8k ? 51 ? 2w out nominal bandwidth = 10mhz t r = 35ns figure 14. wideband output amplifier 6 3 2 4 7 + CA3140 - voltage reference voltage adjustment regulated output input figure 15. basic single supply voltage regulator showing voltage follower CA3140, CA3140a
13 a small heat sink versawatt transistor is used as the series pass element in the fold back current system, figure 17, since dissipation levels will only approach 10w. in this system, the d2201 diode is used for current sampling. foldback is provided by the 3k ? and 100k ? divider network connected to the base of the current sensing transistor. both regulators provide better than 0.02% load regulation. because there is constant loop gain at all voltage settings, the regulation also remains constant. line regulation is 0.1% per volt. hum and noise voltage is less than 200 v as read with a meter having a 10mhz bandwidth. figure 18a shows the turn on and turn off characteristics of both regulators. the slow turn on rise is due to the slow rate of rise of the reference voltage. figure 18b shows the transient response of the regulator with the switching of a 20 ? load at 20v output. figure 16. regulated power supply figure 17. regulated power supply with ?foldback? current limiting 5v/div., 1s/div. figure 18a. supply turn-on and turnoff characteristics top trace: output voltage; 200mv/div., 5 s/div. bottom trace: collector of load switching transistor, load = 1a; 5v/div., 5 s/div. figure 18b. transient response figure 18. waveforms of dynamic characteristics of power supply currents shown in figures 16 and 17 1 3 75 ? 3k ? 100 ? 2 1k ? 1k ? d2201 current limiting adjust 2n6385 power darlington 2 1k ? 1 3 8 2n2102 1k ? +30v input 4 CA3140 7 1 6 5 100k ? 2 3 180k ? 56pf 1k ? 82k ? 250 f + - 0.01 f 100k ? 14 10 6 9 8 50k ? 13 5 f + - 12 ca3086 2.2k ? 3 1 5 4 62k ? voltage adjust 10 f + - 2.7k ? 1k ? 11 7 2 hum and noise output <200 v rms (measurement bandwidth ~ 10mhz) line regulation 0.1%/v load regulation (no load to full load) <0.02% output 0.1 ? 24v at 1a 1 2 1k ? 200 ? d2201 ?foldback? current limiter 2n5294 3k ? 8 2n2102 1k ? +30v input 4 CA3140 7 1 6 5 100k ? 2 3 180k ? 56pf 1k ? 82k ? 250 f + - 0.01 f 100k ? 14 10 6 9 8 50k ? 13 5 f + - 12 ca3086 2.2k ? 3 1 5 4 62k ? voltage adjust 10 f + - 2.7k ? 1k ? 11 7 2 hum and noise output <200 v rms (measurement bandwidth ~ 10mhz) line regulation 0.1%/v load regulation (no load to full load) <0.02% output ? 0v to 25v 25v at 1a 3 100k ? ?folds back? to 40ma 100k ? CA3140, CA3140a
14 tone control circuits high slew rate, wide bandwidth, high output voltage capability and high input impedance are all characteristics required of tone control amplifiers. two tone control circuits that exploit these characteristics of the CA3140 are shown in figures 19 and 20. the first circuit, shown in figure 20, is the baxandall tone control circuit which provides unity gain at midband and uses standard linear potentiometers. the high input impedance of the CA3140 makes possible the use of low- cost, low-value, small size capacitors, as well as reduced load of the driving stage. bass treble boost and cut are 15db at 100hz and 10khz, respectively. full peak-to-peak output is available up to at least 20khz due to the high slew rate of the CA3140. the amplifier gain is 3db down from its ?flat? position at 70khz. figure 19 shows another tone control circuit with similar boost and cut specifications. the wideband gain of this circuit is equal to the ultimate boost or cut plus one, which in this case is a gain of eleven. for 20db boost and cut, the input loading of this circuit is essentially equal to the value of the resistance from terminal no. 3 to ground. a detailed analysis of this circuit is given in ?an ic operational transconductance amplifier (ota) with power capability? by l. kaplan and h. wittlinger, ieee transactions on broadcast and television receivers, vol. btr-18, no. 3, august, 1972. figure 19. tone control circuit usin g ca3130 series (20db midband gain) figure 20. baxandall tone control circuit using CA3140 series 4 7 + CA3140 - +30v 3 2 0.1 f 6 0.005 f 0.1 f 2.2m ? 2.2m ? 5.1 m ? 0.012 f0.001 f 0.022 f 2 f 18k ? 0.0022 f 200k ? (linear) 100 pf 100pf boost treble cut boost bass cut 10k ? 1m ? ccw (log) 100k ? tone control network for single supply - + +15v 3 0.1 f 0.005 f 5.1m ? 0.1 f -15v 2 6 7 4 + CA3140 - tone control network for dual supplies notes: 5. 20db flat position gain. 6. 15db bass and treble boost and cut at 100hz and 10khz, respectively. 7. 25v p-p output at 20khz. 8. -3db at 24khz from 1khz reference. 4 7 + CA3140 - +32v 3 0.1 2.2m ? 2.2 m ? for single supply f 6 2 0.1 f 20pf 750 pf 750 pf 2.2m ? 0.047 f boost treble cut 51k ? 5m ? (linear) 51k ? tone control network boost bass cut 240k ? 5m ? (linear) 240k ? +15v 3 0.1 f 0.047 f 0.1 f -15v 2 6 7 4 + CA3140 - for dual supplies ????: 9. 15db bass and treble boost and cut at 100hz and 10khz, respectively. 10. 25v p-p output at 20khz. 11. -3db at 70khz from 1khz reference. 12. 0db flat position gain. tone control network CA3140, CA3140a
15 wien bridge oscillator another application of the CA3140 that makes excellent use of its high input impedance, high slew rate, and high voltage qualities is the wien bridge sine wave oscillator. a basic wien bridge oscillator is shown in figure 21. when r 1 = r 2 = r and c 1 = c 2 = c, the frequency equation reduces to the familiar f = 1/(2 rc) and the gain required for oscillation, a osc is equal to 3. note that if c 2 is increased by a factor of four and r 2 is reduced by a factor of four, the gain required for oscillation becomes 1.5, thus permitting a potentially higher operating frequency closer to the gain bandwidth product of the CA3140. oscillator stabilization takes on many forms. it must be precisely set, otherwise the amplitude will either diminish or reach some form of limiting with high levels of distortion. the element, r s , is commonly replaced with some variable resistance element. thus, through some control means, the value of r s is adjusted to maintain constant oscillator output. a fet channel resistance, a thermistor, a lamp bulb, or other device whose resistance increases as the output amplitude is increased are a few of the elements often utilized. figure 22 shows another means of stabilizing the oscillator with a zener diode shunting the feedback resistor (r f of figure 21). as the output signal amplitude increases, the zener diode impedance decreases resulting in more feedback with consequent reduction in gain; thus stabilizing the amplitude of the output signal. furthermore, this combination of a monolithic zener diode and bridge rectifier circuit tends to provide a zero temperature coefficient for this regulating system. because this bridge rectifier system has no time constant, i.e., thermal time constant for the lamp bulb, and rc time constant for filters often used in detector networks, there is no lower frequency limit. for example, with 1 f polycarbonate capacitors and 22m ? for the frequency determining network, the operating frequency is 0.007hz. as the frequency is increased, the output amplitude must be reduced to prevent the output signal from becoming slew- rate limited. an output frequency of 180khz will reach a slew rate of approximately 9v/ s when its amplitude is 16v p-p . simple sample-and-hold system figure 23 shows a very simple sample-and-hold system using the CA3140 as the readout amplifier for the storage capacitor. the ca3080a serves as both input buffer amplifier and low feed-through transmission switch (see note 13). system offset nulling is accomplished with the CA3140 via its offset nulling terminals. a typical simulated load of 2k ? and 30pf is shown in the schematic. in this circuit, the storage compensation capacitance (c 1 ) is only 200pf. larger value capacitors provide longer ?hold? periods but with slower slew rates. the slew rate is: note: 13. an6668 ?applications of the ca3080 and ca 3080a high performance operational transconductance amplifiers?. notes: f 1 2 r 1 c 1 r 2 c 2 ------------------------------------------ - = a osc 1 c 1 c 2 ------- r 2 r 1 ------ - ++ = a cl 1 r f r s ------- - + = c 1 r 2 r 1 c 2 output r f r s + - figure 21. basic wien bridge oscillator circuit using an operational amplifier 8 5 4 3 1 9 6 ca3109 diode array +15v 0.1 f 0.1 f -15v 2 6 7 4 + CA3140 - substrate of ca3019 0.1 f 7 7.5k ? 3.6k ? 500 ? output 19v p-p to 22v p-p thd <0.3% 3 r 2 c 2 1000pf 1000 pf c 1 r 1 r 1 = r 2 = r 50hz, r = 3.3m ? 100hz, r = 1.6m ? 1khz, r = 160m ? 10khz, r = 16m ? 30khz, r = 5.1m ? 2 figure 22. wien bridge oscillator circuit using CA3140 +15v 3.5k ? 30pf 2 6 1 + CA3140 - simulated load not required 100k ? input 0.1 0.1 f f 7 0.1 f -15v 2k ? 3 400 ? 200pf 6 4 5 7 4 + ca3080a - 0.1 f +15v -15v 200pf 2k ? 2 3 5 2k ? strobe sample hold -15 0 30k ? 1n914 1n914 2k ? c 1 figure 23. sample and hold circuit dv dt ------ i c --- - 0.5ma 200pf ? 2.5v s ? == = CA3140, CA3140a
16 pulse ?droop? during the hold interval is 170pa/200pf which is 0.85 v/ s; (i.e., 170pa/200pf). in this case, 170pa represents the typical leakage current of the ca3080a when strobed off. if c 1 were increased to 2000pf, the ?hold-droop? rate will decrease to 0.085 v/ s, but the slew rate would decrease to 0.25v/ s. the parallel diode network connected between terminal 3 of the ca3080a and terminal 6 of the CA3140 prevents large input signal feedthrough across the input terminals of the ca3080a to the 200pf storage capacitor when the ca3080a is strobed off. figure 24 shows dynamic characteristic waveforms of this sample-and-hold system. current amplifier the low input terminal current needed to drive the CA3140 makes it ideal for use in current amplifier applications such as the one shown in figure 25 (see note 14). in this circuit, low current is supplied at the input potential as the power supply to load resistor r l . this load current is increased by the multiplication factor r 2 /r 1 , when the load current is monitored by the power supply meter m. thus, if the load current is 100na, with values shown, the load current presented to the supply will be 100 a; a much easier current to measure in many systems. note that the input and output voltages are transferred at the same potential and only the output current is multiplied by the scale factor. the dotted components show a method of decoupling the circuit from the effects of high output load capacitance and the potential oscillation in this situation. essentially, the necessary high frequency feedback is provided by the capacitor with the dotted series resistor providing load decoupling. full wave rectifier figure 26 shows a single supply, absolute value, ideal full- wave rectifier with associated waveforms. during positive excursions, the input signal is fed through the feedback network directly to the output. simultaneously, the positive excursion of the input signal also drives the output terminal (no. 6) of the inverting amplifier in a negative going excursion such that the 1n914 diode effectively disconnects the amplifier from the signal path. during a negative going excursion of the input signal, the CA3140 functions as a normal inverting amplifier with a gain equal to -r 2 /r 1 . when the equality of the two equations shown in figure 26 is satisfied, the full wave output is symmetrical. note: 14. ?operational amplifiers design and applications?, j. g. graeme, mcgraw-hill book company, page 308, ?negative immittance converter circuits?. top trace: output; 50mv/div., 200ns/div. bottom trace: input; 50mv/div., 200ns/div. top trace: output signal; 5v/div, 2 s/div. center trace: difference of input and output signals through tektronix amplifier 7a13; 5mv/div., 2 s/div. bottom trace: input signal; 5v/div., 2 s/div. large signal response and settling time sampling response top trace: output; 100mv/div., 500ns/div. bottom trace: input; 20v/div., 500ns/div. figure 24. sample and hold system dynamic characteristics waveforms +15v 2 1 100k ? 0.1 f -15v 4 5 7 + CA3140 - 0.1 f 4.3k ? 10k ? 6 3 r 1 power supply 10m ? r 2 i l r 2 r 1 m r l i l x figure 25. basic current amplifier for low current measurement systems CA3140, CA3140a
17 +15v 3 0.1 f 8 5k ? 7 1 5 6 2 r 2 r 1 10k ? r 3 1n914 10k ? 100k ? offset adjust 4 peak adjust 10k ? + CA3140 - 20v p-p input bw (-3db) = 290khz, dc output (avg) = 3.2v gain r 2 r 1 ------ - x r 3 r 1 r 2 r 3 + ---------------------------- - === r 3 xx 2 + 1x ? ----------------- ?? ?? r 1 = for x 0.5 5k ? 10k ? -------------- - r 2 r 1 ------ - == r 3 10k ? 0.75 0.5 ----------- ?? ?? 15k ? == output 0 input 0 figure 26. single supply, absolute value, ideal full wave rectifier with associated waveforms +15v -15v 2 7 4 + CA3140 - 3 0.01 f 0.01 f 6 1m ? noise voltage output 30.1k ? 1k ? r s bw (-3db) = 140khz total noise voltage (referred to input) = 48 v (typ) figure 27. test circuit amplifier (30db gain) used for wideband noise measurement top trace: output; 50mv/div., 200ns/div. bottom trace: input; 50mv/div., 200ns/div. figure 28b. small signal response (measurement made with tektronix 7a13 differential amplifier.) top trace: output signal; 5v/div., 5 s/div. center trace: difference signal; 5mv/div., 5 s/div. bottom trace: input signal; 5v/div., 5 s/div. figure 28c. input-output difference signal showing settling time figure 28. split supply voltage follower test circuit and associated waveforms +15v -15v 2 7 4 + CA3140 - 3 0.1 f 0.1 f 6 0.05 f 2k ? 10k ? 100pf simulated load 2k ? bw (-3db) = 4.5mhz sr = 9v/ s figure 28a. test circuit input CA3140, CA3140a
18 typical performance curves figure 29. open-loop voltage gain vs supply voltage and temperature figure 30. gain bandwidth product vs supply voltage and temperature figure 31. slew rate vs supply voltage and temperature figure 32. quiescent supply current vs supply voltage and temperature figure 33. maximum output voltage swing vs frequency figure 34. common mode rejection ratio vs frequency 125 100 75 50 25 open-loop voltage gain (db) 0 5 10 15 20 supply voltage (v) 125 o c 25 o c t a = -55 o c r l = 2k ? 25 0 gain bandwidth product (mhz) 125 o c 25 o c t a = -55 o c r l = 2k ? 20 10 0 5 10 15 20 supply voltage (v) 25 c l = 100pf 1 125 o c 25 o c t a = -55 o c r l = 2k ? 5101520 supply voltage (v) 25 c l = 100pf 20 15 10 5 0 slew rate (v/ s) 0 7 6 5 4 3 0 5 10 15 20 supply voltage (v) 125 o c t a = -55 o c r l = 25 0 2 1 25 o c quiescent supply current (ma) 25 20 15 10 5 0 output swing (v p-p ) 10k 100k frequency (hz) 1m 4m supply voltage: v s = 15v t a = 25 o c 120 100 80 60 40 20 0 common-mode rejection ratio (db) 10 1 10 2 10 3 10 4 10 5 10 6 10 7 frequency (hz) supply voltage: v s = 15v t a = 25 o c CA3140, CA3140a
19 figure 35. equivalent input noise voltage vs frequency figure 36. power supply rejection ratio vs frequency typical performance curves (continued) supply voltage: v s = 15v t a = 25 o c frequency (hz) 110 1 10 2 10 3 10 4 10 5 equivalent input noise voltage (nv/ hz) 100 10 1 1000 10 2 10 3 10 4 10 5 10 6 10 7 frequency (hz) power supply rejection ratio (db) 100 80 60 40 20 0 +psrr -psrr supply voltage: v s = 15v t a = 25 o c power supply rejection ratio (psrr) = ? v io / ? v s 10 1 CA3140, CA3140a
20 metallization mask layout dimensions in parenthesis ar e in millimeters and are derived from the basic inch dimensions as indicated. grid graduations are in mils (10 -3 inch). the photographs and dimensions represent a chip when it is part of the wafer. when the wafer is cut into chips, the cleavage angles are 57 o instead of 90 with respect to the face of the chip. therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions. 62-70 (1.575-1.778) 4-10 (0.102-0.254) 60 50 40 30 20 10 0 58-66 (1.473-1.676) 50 40 30 20 10 61 0 60 65 CA3140, CA3140a
21 CA3140, CA3140a dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes minmaxminmax a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
22 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com CA3140, CA3140a small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measur ed 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.05320.06881.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.00750.00980.19 0.25 - d 0.18900.19684.80 5.00 3 e 0.14970.15743.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.22840.24405.80 6.20 - h 0.00990.01960.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93

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